例句與造句

1. Locking circuit board support cs - type at richeng
   Pc板隔離柱cs
2. Rccn locking circuit board support cs - type material : ul approved nylon 66 , 94v - 2 by hand to support p . c . b
   使用時(shí)先將基板鉆孔4 . 8mm后將隔離柱固定，再將p . c .板套入即可。
3. Dds is used to achieve fine resolution , while injection phase lock circuit is used to realize low phase noise high performance input reference frequency
   Dds用于實(shí)現(xiàn)小步進(jìn),而注入鎖相電路則用來(lái)產(chǎn)生低相噪的高性能參考源。
4. Lut was replaced by the method taking triangle wave and differential in the line phase locked circuit , so it saves the hardware area and cost
   在行鎖相中,用取三角波然后差分的方法替換了查找表,減小了芯片面積,降低了成本。
5. Arranged signal activating lock circuit and time - base control circuit in the sound wave receiving circuit to take the initial signal of back wave as the valid one in the cycle , thus to improve the ratio of signal vs . noise and detective precision
   在超聲波接收電路中設(shè)有信號(hào)觸發(fā)鎖定電路和時(shí)基控制電路。實(shí)現(xiàn)以各探頭中最早收到的回波信號(hào)為本檢測(cè)單元的有效信號(hào)，有效提高信噪比和檢測(cè)精度； 4
6. It's difficult to find locking circuit in a sentence. 用locking circuit造句挺難的
7. Then according to the emphasis of the design , went deeply into the theory of pll frequency synthesizers widely used , described pll ’ s working principle , structure and several types in detail , and made research and analysis of pll frequency synthesizers ’ phase noise , including the effect of the active loop filter on the phase noise , and give some methods to make improvement as well , such as changing loop filter form , reducing divide number , and increase phase detector frequency , etc . then paper introduced the principle character and phase noise analysis of direct digital frequency synthesizer ( dds ) and injection phase lock circuit , which are also important circuits in the design
   論文首先對(duì)幾十年頻率合成器的發(fā)展進(jìn)行概述,而后針對(duì)本次設(shè)計(jì)的重點(diǎn),對(duì)應(yīng)用較為廣泛的鎖相頻率合成理論進(jìn)行了深入的探討,詳細(xì)介紹了鎖相環(huán)的工作原理、組成結(jié)構(gòu)和鎖相類型,并對(duì)鎖相頻率合成器的相噪特性進(jìn)行了研究分析,包括有源環(huán)路濾波器對(duì)于相噪的影響,提出了改善相位噪聲的幾點(diǎn)措施:改善環(huán)路形式、降低分頻數(shù)、增大鑒相頻率等。接著介紹了直接數(shù)字頻率合成器( dds )和注入鎖相電路的原理特點(diǎn)以及相噪分析,它們也是本次設(shè)計(jì)的重要電路。
8. The clock recovery block of usb2 . 0 transceiver macrocell consists of phase locked circuit , such as pll and dll ( delay locked loop ) . this block use external crystal 12mhz sin signal to produce 60mhz , 120mhz , 480mhz clock signal , and can recover colock signal form date wave . it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2 . 0 specification .
   目的是用鎖相環(huán)電路? pll和dll (延遲鎖相環(huán))實(shí)現(xiàn)usb2 . 0收發(fā)器宏單元utm的時(shí)鐘恢復(fù)模塊。其中pll環(huán)路構(gòu)成的時(shí)鐘發(fā)生器將外部晶振的12mhz正弦信號(hào)生成60mhz 、 120mhz 、 480mhz等本地時(shí)鐘信號(hào)。 dll環(huán)路依據(jù)本地時(shí)鐘信號(hào)對(duì)外部數(shù)據(jù)信號(hào)進(jìn)行時(shí)鐘恢復(fù)。